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Product description: Sipeed Tang Nano - FPGA development plate GW1N-1
Development board based on the GW1N-1-LV chip,which has 1152LUT4 with 4RAMaddressesand 864 FF (Flip-Flop).The module has72 kb of SRAM memory. Due to its small size the board does not have a DSP module, so complex calculations such as accumulation are not possible. It is equipped with 34I/Opins.The board is powered by aUSB Cconnector.
Sipeed Tang Nano backbone.
Sipeed Tango Nano is programmed via the JTAG interface using USB, without the need for an additional downloader. Built-in40-pin FPCconnector allows to connectthe display.
Main features of Sipeed Tango Nano board
- The deal: GW1N-1-LV with 1152 LUT4 and 864 FF
- 72 kb SRAM, 96 kb flash memory
- 40-pin FPC connector for display connection
- Built-in JTAG downloader
- Does not support DSP
- Small dimensions: 58.34 x 21.29 mm
Dimensions of Sipeed Tang Nano.
Specifications of Sipeed Tang Nano tiles
- The deal: GWIN-1-LV:
- LUT4: 1152
- Flip-Flop: 864
- SRAM: 72 kb
- Flash: 96 kbp
- PLLs+DLS 1+0
- Core tension: 1,2 V
- Programming: USB
- Power supply: 5 V - USB C
- Current consumption: up to 400 mA
- Power circuit: each Bank has a separate LDO power circuit (except for BANK0/3). I/O level in BANK 1 and BANK 2 can be adjusted by changing the LDO circuit
- Display: 40-pin FPC - built-in display backlight controller
- I/O: 32-pin
- PSRAM memory: 64 Mb 3.3 V
- LEDs: built-in RGB LEDs
- Button: 2 buttons 3 x 4 mm
- Quartz: built-in 24 MHz quartz oscillator
- Operating temperature: -30°C to 50°C
- Dimensions: 58.34 x 21.29 mm
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